TECH

Investing in Advanced Semiconductor Materials

Witawat (Ed) Wijaranakula, Ph.D.
Wed Jul 7, 2004

High-Speed and Less Power Consumption: Strained SiGe (silicon germanium) technology, pioneered by IBM Microelectronics (NYSE:IBM), was first introduced into high-volume bipolar chip production in 1989 and is now standard in the manufacturing of chips used in high-data-rate wireless local area network (WLAN) products. In this technology, a nano-layer of SiGe is deposited on a silicon substrate wafer at high temperatures. Compressive stresses induced by Ge atoms reduce the energy bandgap, which in turn increases electron mobility across the transistor channel. 

Because manufacturing of defect-free SiGe wafers requires precise control of the SiGe deposition process, development and production costs of SiGe wafers is high.

Last year, United Microelectronics Corporation (NYSE-ADR:UMC), Taiwan’s second largest semiconductor foundry, introduced its strained silicon technology in its high performance CMOS chip process using wafers supplied by privately-owned AmberWave Systems, a small silicon supplier based in Salem, NH. UMC claimed that its strained silicon process exhibited significant CMOS performance enhancement, with over 20% current driving capability successfully demonstrated on a 70-nm strained silicon transistor and speed enhancement of over 10% on a test circuit.

The large-volume commercial silicon wafer supplier MEMC Electronic Materials, is now investing in new developments by signing an agreement with the Inter-university MicroElectronics Center (IMEC) in Leuven, Belgium to license advanced IMEC strained silicon technology. The licensing agreement will allow MEMC to produce blanket strained silicon substrate wafers using IMEC's thin strain relaxed buffer (SRB) technology. By participating in the program, MEMC researchers work within IMEC, in cooperation with researchers from several semiconductor device manufacturers, for the goal of improved device performance by implementing strained silicon in the transistor channel regions. 

Silicon-On-Insulator (SOI): In sub-100nm technology, CPU manufacturers, including Advanced Microdevices (NYSE:AMD), are using SOI wafers as starting materials because it is possible to design a SOI circuit with up to 30 percent faster transistor operation than the current MOS circuit built on silicon. Typical commercial SOI wafers consist of a thin silicon top layer, > 50nm, and a bottom silicon substrate wafer having a thickness of several hundred microns. The top silicon layer and substrate wafer are separated (insulated) by a thin oxide layer of ~ 150nm thick. 

SOI wafers are manufactured using either a Separation by Implantation of Oxygen (SIMOX) or Smart Cut™ processes. Both processes, which are fundamentally different from each other, involve intense research and development work as well as high set-up and production costs. Because of its premium price, the SOI wafer market is still relatively small compared to that of silicon and epitaxial wafers, ~ $5 billion last year. The demand for SOI wafers is expected to increase as the wafer price becomes economically feasible for the mass production of low-cost chips.

Danvers, MA-based Ibis Technology (NASDAQ:IBIS), which specializes in SIMOX wafers, sells their SOI wafers to customers including IBM (92% of sales) and China-based Shanghai Simgui. Last year, the company had a revenue of $18.4 million from sales of wafers and equipment used for the SOI wafer manufacturing. Ibis recently formed a marketing alliance with MEMC Electronic Materials, which is also its primary supplier of silicon wafer substrates.

Bernin, France-based Soitec is the world's leading manufacturer of SOI wafers based on the Smart Cut™ approach. The company's first strategic licensing partner was Shin-Etsu Handotai, which already began production of Smart Cut™ SOI wafers for shipment to third-party customers. Last year, the company set up its pilot line facility to produced full Smart Cut™ strained SiGe on insulator wafers (SGOI). The SGOI process was first developed by IBM in 2002 for use in making high-performance chips at the 65-nm node. Soitec, which is traded on the French "Nouveau Marche" at the Paris Stock Exchange, had a revenue of $109 million in 2003. ($1.28 = 1 Euro).

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