Nanotechnology, manipulating materials at the nanometer scale, is a largely emerging area of research and development for electronics companies with new products or improvements on pre-existing devices and materials already on the market. Two promising technologies, carbon nanotubes (CNTs) and silicon nanowires (SiNWs), are being evaluated for potential use in future integrated nanocircuits. Unknown factors including the properties of atomic-scale intrinsic defects in CNTs and SiNWs, the high cost of manufacturing and process integration as well as issues related to device integrity and reliability could delay the deployment of such technologies into a mass production scale well beyond the year 2010. 

Start-up companies like Woburn, MA-based Nantero, Inc., is developing a new type of carbon nanotube-based nonvolatile random access memory NRAM™ chip which may someday replace the pre-existing silicon-based dynamic DRAM, static SRAM and flash memory. Business Communications Co., a Norwalk, CT-based industrial research and market analysis company, forecasts that the worldwide non-volatile memory market is expected to be $17.4 billion this year and could reach $50 billion by 2010. Nantero is partially funded by Harris & Harris Group, a publicly traded New York, NY-based venture capital company (NASDAQ: TINY).

Large companies, such as Intel Corporation (NASDAQ: INTC), IBM (NYSE: IBM), Fujitsu (TSE:6702), NEC (TSE:6701), Infineon Technologies AG (FSE/NYSE: IFX) and Samsung Electronics (KRX:005930), with well-funded research programs are also stepping up development of electronic products that include nanotechnology to enhance the performance of existing processor and memory devices. Nevertheless, Dr. Robert R. Doering, Senior Fellow at Texas Instruments Inc. (NYSE:TXN) expressed a cautious comment in an interview with the EE Times earlier this year that, "What's called nanotechnology today depends on what you're trying to advertise, sell or get funding for."

Clock is Ticking, but Slowly.  Thus far, Moore's Law, in which the number of transistors on a given chip is said to have to double every 18 to 24 months, has helped chip makers to introduce higher performance chips and to maintain high operating margins. Chip makers are consistently moving to less expensive process technologies and smaller device geometries by shrinking the channel which connects the source and the drain of silicon-based transistors in microprocessors.

The transistor channel allows current to flow from the source to the drain, representing a binary "1" in digital computing. When current is not flowing, the transistor is read as a "0". A shorter channel length means a higher operating speed as well as more transistors that can be packed on a given chip and a higher operating profit. According to the technology road map of the Semiconductor Industry Association (SIA), the ability to shrink the channel will hit physical limits sometime before the year 2020. At that point, new  revolutionized chip design architectures or materials are needed.

Early this year, Fujitsu announced that in 2010, the company could begin using carbon nanotubes to replace some of the copper interconnections in their chips made on the 45-nanometer process. Dr. Yuji Awano, a research fellow at Fujitsu Laboratories' Nanotechnology Research Center, explained that in theory, carbon nanotubes can have an electrical current density about 1,000 times higher than that in copper and hence the carbon nanotube interconnection can be made smaller than that made with copper. In addition, electrons can flow through carbon nanotubes about 10 times faster than that in copper and dissipate heat much more readily.

Dr. Yukinori Ochiai, principal researcher at Toyko, Japan-based NEC's nanotechology group, has been developing a new type of CNT-based Field-Effect Transistor (CNTFET) having an aluminum gate electrode and titanium dioxide gate insulator. According to Ochiai, such a CNTFET can amplify about 20 times more current than conventional metal oxide silicon-based transistors (MOSFET) with low leakage between the gate and other parts of the transistor. The next step is to make this CNTFET in a group of 10 and then hundreds, explained Dr. Ochiai. 

For reference, the latest Intel 64-bit microprocessor, Itanium-2, has 1.72 billion transistors on a single chip. Our analysis shows that more billion transistor chips like NAND flash memory could enter the chip market in the second half of next year.

Commercially Viable Products Still a Decade Away.  Santa Clara, CA-based chip giant, Intel Corporation (NASDAQ: INTC), is sticking with the silicon complementary metal oxide semiconductor (CMOS) infrastructure for the next 10 years at least, but is planning the future of processors with nanotechnology. As the physical channel length shrinks to 15 nm and the gate oxide to a thickness of less than 1 nm early next decade, Intel may be forced to deploy a nonplanar-type CMOS structures, such as tri-gate transistors, where the gate material surrounds the transistor on three sides.

Intel is also investing in start-up companies such as privately held Palo Alto, CA based-Nanosys Inc through Intel Capital, the strategic investment group at Intel Corp. The corroboration includes an exploration of next-generation materials such as nanowires in non-volatile memory technology applications. Nanosys was recently issued a U.S. Patent No. 6,882,051 entitled "Nanowires, nanostructures and devices fabricated therefrom," by the U.S. Patent and Trademark Office. 

Considering other risk factors including development costs of design, manufacturing and inspection tools, manufacturing process costs and yields as well as the stability of chip pricing, it could be at least another decade until nanotubes and nanowires are materials that come into use in the mass production of nanoelectronic devices.